This invention is related to digital circuit designs, and more particularly, to digital circuit designs having phase alignment circuit.
Delayed locked loops are frequently employed in high-speed phase alignment circuits such as Double Date Rate Synchronous DRAM (DDR SDRAM). In a system using DDR SDRAM as a memory storage device, data strobe phase control is needed in order to latch the read data returned from the DDR SDRAM (hereinafter, DDR). The data strobe and the data is xe2x80x9cedge alignedxe2x80x9d when the DDR is returning the read data, while the data strobe and the data is xe2x80x9ccenter-alignedxe2x80x9d when DDR is performing write cycles. The different methodologies respectively for read and write cycles are for purpose of simpler design and better yield in DDR manufacturing. Hence, a precise quarter-period delay is used to center-align the strobe and the data when the DDR is performing the write cycle.
FIG. 1 shows a typical DLL circuit. The phase detector 130 compares the ext_clk signal with the delay_clk signal generated by the T/4 delay line 115. The delay line monitor 140, responsive to the increment_or_decrement signal from the phase detector 130, adjusts the amount of delay by outputting the delay_control_number signal to the delay line 115 and 116. Consequently, the system converges and the T/4 delayed clock 150 is obtained. However, the result from the phase detector 130 may shift due to variation of the temperature, causing the delay line monitor 140 to provide inappropriate information to the T/4 delay line 115 and 116. Moreover, process variation may also affect the result from the phase detector 130. Therefore, the present invention proposes a digital delayed locked loop circuit with double lock mechanism and dynamic delay control to solve the problems mentioned above. It should be noted that the present invention can generate any desired delay signal. So it is applicable in any circuit using DLL mechasim.
This invention presents a precise time delay generator using a dual-rail digital delay-locked loop (DLL). The dual-rail digital DLL includes a first delay line, a second delay line, a delay unit, a first phase detector, a second phase detector, a delay line monitor, a digital-to-time converter (DTC) delay unit.
The first delay line receives an external clock signal and a first delay control signal to generate a first delay signal. And the second delay line receives a second delay control signal and the external clock signal to generate a second delay signal. The delay unit generates an internal delay signal using the external clock signal, the first delay signal and the second delay signal. The first phase detector receives the internal delay signal and the first delay signal to generate a first control signal, and the second phase detector uses the internal delay signal and the second delay signal to generate a second control signal. The delay line monitor generates the first delay control signal and the second delay control signal, in response to the first and the second control signal. The delay signal is generated by the DTC delay unit, which inputs the external clock signal and the first delay control signal.
This present invention provides a dual rail delayed locked loop in order to generate desired delay signal. The dual-rail DLL design introduced herein dynamically changes the delay of the DTC delay unit due to variation of the voltage and temperature. This circuit provided can be employed in any high-speed phase alignment system, and the amount of delay can be easily extended to 1/N period time by introducing N DTC delay units to the delay lines.